1. Field of the Invention
The present invention relates to a demodulation device for a four phase modulated wave, more particularly to a Costas loop carrier recovery circuit which is suitably formed on a semiconductor integrated circuit and is excellent in a linearity.
2. Description of the Related Art
Since a digital phase modulation method for a carrier wave called a PSK (Phase Shift Keying) method is generally superior in its predetermined band characteristic and error ratio characteristic to other methods such as amplitude modulation, frequency modulation and bias modulation, the digital phase modulation method has been widely used for microwave digital communication using a microwave pulse code modulation, satellite broadcast communication and data transmission modems. The PSK method in which a phase is shifted by .pi./4 has been used also in digital mobile communication, and it is becoming more popular.
In this quadriphase PSK method, digital codes of signals to be transmitted are partitioned every two bits and the carrier waves are modulated depending on a quantity of phase variations which correspond to these four combinations. In the majority of the quadriphase PSK methods put into practical uses, the quantities of phase variations 0, .pi./2, .pi., and 3.pi./2 correspond to the four combinations (0, 0), (0, 1), (1, 0) and (1, 1), respectively.
Therefore, since two bit signal components are included in a common mode component I and an orthogonal component Q of the carrier wave, respectively, it is sufficient that the common mode component and the quadrature component of the carrier wave are detected in order to judge plus and minus of them when they are demodulated.
A synchronous detection method as the detection method in case where the common mode and orthogonal components are detected produces low noise and is excellent in an error ratio characteristic so that it is frequently used. Unlike other delay detection methods, it is necessary that a carrier wave recovery circuit be provided on a receiving side to generate a carrier wave having a correct phase.
This carrier wave recovery circuit is constituted as a circuit which is designed such that a phase synchronous circuit constituted by a PLL (Phase Locked Loop) is controlled by a signal obtained by removing a sign component from an input carrier wave.
FIG. 1 is a block diagram showing a constitution of a conventional Costas loop carrier recovery circuit.
Referring to FIG. 1, reference numerals 1, 2 and 17 denote multipliers; 3, 4 and 8, low pass filters (LPFs ); 15, an adder; 16, a subtracter; 9, a voltage controlled x'tal oscillator (VCXO); and 10, a phase shifter, respectively.
A signal of the quadriphase modulated wave is expressed as the following equation (1), when .omega.t is a frequency of the carrier wave and phases of .THETA. is shifted by 0, .pi./2, .pi. and 3.pi./2, respectively. EQU S=E cos(.omega.t+.THETA.) (1)
Furthermore, when two outputs from the VCXO 9 are assumed to be signals A and B, one of the signals A and B being an output obtained by shifting the phase of the other by .pi./2 by the phase shifter 10, the signals A and B are expressed by the following equations (2) and (3). EQU A=E.sub.1 sin(.omega.t+.THETA..sub.1) (2) EQU B=E.sub.1 cos(.omega.t+.THETA..sub.1) (3)
When a quadriphase modulation wave S and the oscillator outputs A and B are demodulated by the multiplication circuits 1 and 2 and then pass through the LPFs 3 and 4, an output from the multiplier 1 is expressed by the following equation (4). EQU E cos(.omega.t+.theta.).times.E.sub.1 sin(.omega.t+.theta..sub.1) ##EQU1##
When the output from the multiplier 1 is allowed to pass through the LPF 3, an alternation current component is removed. The following equation (5) is obtained. ##EQU2##
Similarly, the output from the multiplier 2 is obtained by multiplying the equation (1) with the equation (3) as shown by the following equation (6). ##EQU3##
When the output from the multiplier 2 is allowed to pass through the LPF 4, the following equation (7) is obtained. ##EQU4##
A computation circuit disposed after the outputs of the LPFs 3 and 4 is a Costas loop carrier recovery circuit, which keeps the phase of an output signal from the VCXO 9 constant whichever phase state (0, .pi./2, .pi. and 3.pi./2) the quadriphase modulated wave of the input carrier wave may take.
Supposing that the demodulated signal of the equation (5) is P and the signal of the equation (7) is Q, the output point E of the adder circuit 15 outputs P+Q; the output point F of the subtracting circuit 16, P-Q; and the output G of the multiplying circuit 17, P.times.Q.times.(P+Q).times.(P-Q). Furthermore, the following equations (8) and (9) are given. ##EQU5##
Therefore, at the output point G of the four level multiplier, the following equation can be obtained from the equation (8).times.the equation (9). ##EQU6##
This implies that the phase difference between the quadriphase modulation wave and the output signal from the VCXO 9 is n.pi./4 (n: integer), the output voltage becomes relatively zero, and the PLL is locked at this state.
Consequently, when this output G is allowed to return to the VCXO 9 through the LPF 8, data of the signals P and Q will be demodulated.
However, in the constitution of the conventional quadriphase demodulation circuit shown in FIG. 1, although the four level multiplier for multiplying the quadrisignals is shown as the multiplier 7, it can not be prevented that the size thereof will be large as disclosed, for example, in U.S. Pat. No. 4,694,204.
Specifically, the above-described conventional Costas loop carrier recovery circuit has a drawback that it employs many multiplying circuits so that a size thereof will be large.